Field of the Invention
The invention relates to a memory cell array having memory elements with magnetoresistive effect and a method for manufacturing it.
Technologie Analyse XMR-Technologien, Technologie-frxc3xch-erkennung [Technology Analysis XMR Technologies, Early Recognition of Technology], by Stefan Mengel, Publisher VDI-Technologiezentrum Physikalische Technologie, discloses layered structures with magnetoresistive effect. Depending on its design, the layered structure is classified as a GMR (giant magnetoresistance) element, TMR (tunneling magnetoresitive) element, AMR (anisotropic resistance) element or CMR (colossal magnetoresistance) element. The term GMR element is used in the art to designate layered structures which have at least two ferromagnetic layers and a nonmagnetic, conductive layer arranged between them and exhibit the GMR (giant magnetoresistance) effect, that is to say exhibit a large magnetoresistive effect in comparison with the AMR (anisotropic magnetoresistance) effect. The GMR effect is understood as referring to the fact that the electrical resistance of the GMR element is dependent on whether the magnetizations in the two ferromagnetic layers are oriented in parallel or antiparallel both for currents which are parallel (CIP current in plane) and perpendicular (CPP current perpendicular to plane) to the layer planes. The resistance changes here as a function of the orientation of the magnetizations by xcex94R/R=5 percent to 20 percent at room temperature.
The term TMR element is used in the specialist field for xe2x80x9cTunneling Magnetoresistancexe2x80x9d layered structures which have at least two ferromagnetic layers and an insulating, nonmagnetic layer arranged between them. The insulating layer has such a small thickness that a tunnel current occurs between the two ferromagnetic layers. These lead structures also exhibit a magnetoresistive effect which is brought about by spin-polarized tunnel current through the insulating, nonmagnetic layer arranged between the two ferromagnetic layers. In this case also, the electrical resistance of the TMR element (CPP arrangement) is dependent on whether the magnetizations in the two ferromagnetic layers are oriented in parallel or antiparallel. The resistance varies by xcex94R/R=10 percent to approximately 30 percent at room temperature.
The AMR effect is due to the fact that the resistance in magnetized conductors parallel to the magnetization direction varies from that of magnetized conductors which are perpendicular to the magnetization direction. It is a volume effect and thus occurs in ferromagnetic single layers.
A further magnetoresistive effect which is referred to as colossal magnetoresistance effect due to its magnitude (xcex94R/R=100 percent to 400 percent at room temperature) requires a high magnetic field for switching between the magnetization states owing to its high coercitive forces.
It has been proposed (see for example D. D. Tang, P. K. Wang, V. S. Speriosu, S. Le, K. K. Kung, xe2x80x9cSpin Valve RAM Cellxe2x80x9d, IEEE Transactions on Magnetics, Vol. 31, No. 6, November 1996, page 3206) to use GMR elements as memory elements in a memory cell array. The magnetization direction of the one ferromagnetic layer of the GMR element is held here, for example, by an adjacent antiferromagnetic layer. Intersecting x and y lines are provided. In each case a memory element is arranged at the points of intersection of the x/y lines. In order to write information, the x/y lines are supplied with signals which bring about at the point of intersection a magnetic field which is sufficient for the change of polarity. In order to read out the information, the x/y lines can be supplied with a signal which switches the respective memory cell to and fro between the two magnetization states. The current through the memory element from which the resistance value, and thus the information, is determined is measured.
In order to write and read, local magnetic fields of 10 Oe to approximately 100 Oe corresponding to 8 A/cm to 80 A/cm are necessary. It is desirable here for the magnetic fields to be generated by the smallest possible current in the lines.
However, as miniaturization progresses, the current densities necessary to generate the local magnetic fields become greater. In addition, an effect has been observed (see M. H. Kryder, Kie Y. Ahn, N. J. Mazzeo, S. Schwarzl, and S. M. Kane, xe2x80x9cMagnetic Properties and Domain Structures in Narrow NiFe Stripesxe2x80x9d, IEEE Transactions on Magnetics, Vol. Mag.-16, No. 1, January 1980, page 99), in which the magnetic switching field thresholds increase as the dimensions become smaller, that is to say higher currents become necessary for switching.
It is accordingly an object of the invention to provide a memory cell array and a method for manufacturing the memory cell array which overcomes the above-mentioned disadvantageous of the prior art memory cell arrays and methods for producing arrays of this general type. In particular, it is an object of the invention to provide a memory cell array having a memory element with magnetoresistive effect which can be programmed with lower currents and current densities than in the prior art.
With the foregoing and other objects in view there is provided, in accordance with the invention a memory cell array, that includes: a substrate having a main face; a first insulating layer configured on the main face of the substrate, the first insulating layer formed with a trench having a bottom and edges; a first line configured in the trench of the first insulation layer; a second line; a memory element configured at a point of intersection between the first line and the second line, the memory element being switched between the first line and the second line; a first yoke disposed adjacent the bottom and the edges of the trench of the first insulation layer, the first yoke configured such that a magnetic flux through the first yoke is essentially closed in the memory element, the first yoke including a magnetizable material with a relative permeability of at least 10; and a line selected from the group consisting of the first line and the second line being supplied with current during a write access and being partially surrounded by the first yoke.
In other words, at least a first line, a second line and a memory element with magnetoresistive effect which is arranged at a point of intersection between the first line and the second line are provided in the memory cell array. Preferably, the memory element is switched between the first line and the second line. In addition, a yoke is provided which partially surrounds at least one of the lines and which contains magnetizable material with a relative permeability of at least 10. The yoke is arranged in such a way that the magnetic flux path through the yoke is closed essentially by means of the memory element. In order to write to the memory cell, the first line and the second line are supplied with current in such a way that superposition of the magnetic fields of the first line and of the second line at the location of the memory element generates a magnetic field which exceeds the switching threshold of the memory element.
The yoke is magnetized here by the magnetic field of the line through which current flows, the line being partially surrounded by the yoke. As a result, the induction flux density B is increased by a factor xcexcr, the relative permeability. As a result, magnetic poles are produced at the end faces of the yoke and a magnetic field is generated between the poles. This magnetic field assumes very high values depending on the selection of the material of the yoke and is used to switch the memory element. Given identical current density in the line, considerably higher magnetic fields are thus achieved for switching the memory element.
Part of the yoke can be formed from all ferromagnetic and ferromagnetic materials.
The yoke is preferably formed from soft-magnetic, ferromagnetic layers, in particular composed of Fe, Ni, Co, Mn, MnBi, FeSixe2x80x94, FeNixe2x80x94, FeCoxe2x80x94, FeAlxe2x80x94 alloys or soft-magnetic ferrites.
The use of a magnetic flux concentrator in a memory cell array has admittedly already been proposed in U.S. Pat. No. 4,455,626. In the publication a layer in which the magnetization is changed as a function of the information from two adjacent write lines is used as a memory element. In order to read out the information, a magnetoresistive sensor is provided which is arranged below the storage layer together with a read line in the gap of a planar layer, designated as a magnetic shield concentrator, made of magnetizable material. The magnetic flux of the storage layer is concentrated on the magnetoresistive sensor by this magnetic field concentrator. The arrangement is not intended or suitable for increasing the effectiveness of the currents in the linear write lines for the reversal of the polarity of the magnetic storage layer.
All known TMR elements and GMR elements in a CPP arrangement (current perpendicular to plane) are suitable as a memory element in the memory cell array according to the invention. The GMR effect is greater if the current flows perpendicular through the layer stack (CPP) than if the current flows in parallel in the layers (CIP current in plane). Furthermore, all XMR elements which have at least two magnetization states with respectively different resistances that can be obtained by applying a magnetic field whose strength can be tolerated by the memory array are suitable for being switched to and fro. In particular, the use of CMR elements is possible because the necessary magnetic field strengths can be obtained by means of the yoke.
The memory elements preferably each have two ferromagnetic layers and a nonmagnetic, insulating layer (TMR) or conductive layer (GMR) arranged between them. The ferromagnetic layers each have two magnetization states. It is advantageous to use an insulating, nonmagnetic layer (TMR element) because this enables higher element resistances (xe2x89xa7100 Kxcexa9) to be obtained and these are more favorable in terms of the power consumption and signal-to-noise ratio.
One of the ferromagnetic layers is preferably arranged adjacent to an antiferromagnetic layer which fixes the magnetization direction in the adjacent ferromagnetic layer. Materials suitable for the antiferromagnetic layer are, inter alia, materials containing at least one of the elements Fe, Mn, Ni, Cr, Co, V, Ir, Tb and O.
As an alternative, the memory elements can each have two ferromagnetic layers and a nonmagnetic layer arranged between them. One of the ferromagnetic layers is magnetically harder than the other ferromagnetic layer, that is to say, the polarity of only one ferromagnetic layer is reversed, while the other remains unaffected. The nonmagnetic layer may be insulating or noninsulating.
Alternatively, the two ferromagnetic layers are essentially of the same magnetization composition, it being possible to selectively switch over the polarity of the magnetization in one of the ferromagnetic layers by means of the yoke.
Suitable materials for the ferromagnetic layers are, inter alia, those which contains at least one of the element Fe, Ni, Co, Cr, Mn, Gd, Dy. The thickness of the ferromagnetic layers in GMR elements in a CIP arrangement is preferably in the range between 2 and 10 nm. In GMR and TMR elements in a CPP arrangement, the thickness of the ferromagnetic layers may also be greater (for example 100 to 200 nm). Al2O3, MgO, NiO, HfO2, TiO2, NbO or SiO2 are suitable as the insulating material for the nonmagnetic layer which acts as a tunnel insulator. Cu or Ag are suitable as the noninsulating material for the nonmagnetic layer. The thickness of the nonmagnetic layer is in the range between 1 and 4 nm, preferably between 2 and 3 nm.
The memory elements preferably have dimensions in the range between 0.05 xcexcm and 20 xcexcm. They can be, inter alia, of square or elongated shape.
The lines, the memory element and the yoke are preferably contained integrated in a substrate. It is particularly advantageous to use a substrate which includes a carrier wafer, in particular made of semiconductor material, particularly monocrystalline silicon, because in this case the integrated memory cell array can be manufactured with the methods of silicon processing technology. As a result, a high packing density can be achieved in the memory cell array. Furthermore, the periphery can also be integrated in the substrate.
According to one refinement of the invention, the substrate on the carrier wafer has a first insulating layer which is provided with a trench. The first line runs in the trench. The memory element is arranged above the first line and the second line is arranged above the memory element. The yoke partially surrounds either the first line or the second line. If the yoke partially surrounds the first line, it adjoins the sides and the floor of the trench and can be manufactured by means of layer deposition after the formation of the trench in the first insulating layer. If the yoke surrounds the second line, it adjoins the sides and the surface of the second line facing away from the memory element and can be manufactured by layer deposition and spacer etchings.
Preferably, a first yoke and a second yoke are provided which are each embodied like the yoke. The first yoke partially surrounds the first line and the second yoke partially surrounds the second line. Both the first yoke and the second yoke are arranged in such a way that a magnetic flux path through the first yoke or the second yoke is closed essentially by means of the memory element. This configuration has the advantage that both the magnetic field generated by the first line through which current flows and the magnetic field generated by the second line through which current flows bring about a reinforced magnetic field at the location of the memory element by means of the first yoke or the second yoke respectively.
In the memory cell array, the memory cell is selected by means of the first line and the second line between which the memory element is switched. The routing of the first line and of the second line with respect to one another can be both parallel and perpendicular to one another in the vicinity of the memory element. Accordingly, the magnetic fields which are oriented in parallel or magnetic fields which are oriented perpendicularly to one another are superposed at the location of the memory element.
In order to achieve high storage densities it is advantageous to provide a multiplicity of memory elements with a yoke, first lines and second lines. The memory elements, which are preferably arranged in a grid, are each arranged at a point of intersection between one of the first lines and one of the second lines.
Because local magnetic fields which are considerably higher, at least by a factor of 10 to 100, are generated in the memory cell array according to the invention for a given current strength, considerably lower current densities occur in the lines with the same line cross section. The necessary current densities are below the limit defined by electromigration, even given a high degree of miniaturization of the memory cell array.
Because increased local magnetic fields can be achieved with the same current strength, magnetically harder layers, which have a substantially higher coercitive field strength than 10 Oe, may also be used for the memory element. Memory elements made of magnetically harder layers have the advantage that they are less sensitive to external magnetic interference. As a result, less stringent requirements are made on the magnetic field shielding. In addition, the risk of data loss is reduced.
As a result of the lower current densities, it is not necessary to increase the level of the lines, and thus the aspect ratios. The memory cell array is therefore also suitable for stacked arrays in order to increase the storage density.
Due to the lower current strength which is necessary to generate the same magnetic field, the power consumption can be reduced considerably during the writing and reading operations.
With the foregoing and other objects in view there is also provided, in accordance with the invention a method for manufacturing a memory cell array, that includes steps of: applying a first insulating layer to a carrier wafer; producing a trench having side walls and a bottom in the first insulating layer; producing a first yoke that adjoins the side walls of the trench and that adjoins the bottom of the trench, and producing the first yoke from a magnetizable material with a permeability of at least 10; producing a first line in the trench; producing a memory element with magnetoresistive effect above the first yoke and connecting the memory element to the first line; and producing a second line above the memory element and connecting the second line to the memory element.
In accordance with an added mode of the invention, in order to produce the first yoke, a second insulating layer having a trench formed with edges is produced. Spacers are formed on the edges of the trench formed in the second insulating layer, and the spacers are made of a magnetizable material with a permeability of at least 10. The method would also include steps of: producing the second line in the trench formed in the second insulating layer; producing a yoke part from a magnetizable material with a permeability of at least 10; and producing the yoke part to partially cover the second line above the memory element and connecting the yoke part to the spacers such that the spacers and the yoke part form a second yoke.
In accordance with another mode of the invention, the method includes steps of: in order to produce the first yoke, applying a second insulating layer on the carrier wafer; producing a trench having edges in the second insulating layer; forming spacers, made of a magnetizable material with a permeability of at least 10, on the edges of the trench in the second insulating layer; producing the second line in the trench in the second insulating layer; producing a yoke part from a magnetizable material with a permeability of at least 10; and producing the yoke part to partially cover the second line above the memory element and connecting the yoke part to the spacers such that the spacers and the yoke part form a second yoke.
In accordance with a concomitant mode of the invention, the method includes steps of: forming a line selected from the group consisting of the first line and the second line by depositing a metal layer and by performing chemical-mechanical polishing.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a memory cell array and method for manufacturing it, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.